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publication order number: NBLVEP16VR/d ? semiconductor components industries, llc, 2003 december, 2003 ? rev. 2 1 NBLVEP16VR 2.5v/3.3v/5vecl differential receiver/driver with oscillator gain stage and enabled high gain outputs the NBLVEP16VR is an ecl/lvpecl oscillator gain stage with high?gain output buffers, selectable output enable and a feedback buffer. the NBLVEP16VR is a solution for crystal oscillators and saw?based voltage?controlled oscillators. ? q and q outputs have selectable 4 ma or 8 ma, self bias current sources ? qhg and qhg have a selectable 10 ma, self bias current sources ? synchronous output enable of the high?gain outputs with selectable disabled state ? selectable lvcmos/lvttl or lvpecl level input of the output enable pin ? maximum frequency > 2.5 ghz typical ? (lv)pecl mode operating range: v cc = 2.375 v to 5.5 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ?2.375 v to ?5.5 v ? temperature compensated inputs and outputs ? excellent clock input sensitivity ? v bb output supports current source/sink capability up to a robust 1.5 ma q q d d v bb od_mode en figure 1. logic diagram cs_sel qhg v ee qhg v eep en_sel q q 0 1 lvcmos/lvttl threshold 470 470 10 ma ea. (opt.) 4 ma ea. 4 ma ea. (opt.) v bb v bb_adj len latch q d device package shipping 2 ordering information NBLVEP16VRmn qfn?16 123 / rail NBLVEP16VRmnr2 qfn?16 3000/ tape & reel qfn?16 mn suffix case 485g marking diagram http://onsemi.com xxxx xxxx alyw xxxx = device code a = assembly location l = wafer lot y = year w = work week bottom view nbwlvep16vr wafer refer to note 1. 1. contact sales representative. 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d.
NBLVEP16VR http://onsemi.com 2 q q d d v bb od_mode en figure 2. logic diagram cs_sel qhg v ee qhg v eep en_sel q q 0 1 lvcmos/lvttl threshold 470 470 10 ma ea. (opt.) 4 ma ea. 4 ma ea. (opt.) v bb v bb_adj len latch q d table 1. q and q internal current source selector cs_sel q q see figure open 4 ma typical 4 ma typical 13, 13 v ee 8 ma typical 8 ma typical 10, 13 v cc 0 ma 4 ma typical 13, 13 table 2. qhg and qhg internal current source selector v eep qhg qhg see figure open 0 ma 0 ma 8, 11 v ee 10 ma typical 10 ma typical 9, 12 table 3. output enable and output disabled state truth table en_sel 2 od?mode* en* q and q qhg qhg v cc or open low or open lvpecl low, v ee or open data data data v cc or open low or open lvpecl high or v cc data low high v ee low or open lvcmos low, v ee , or open data low high v ee low or open lvcmos high or v cc data data data v cc or open high lvpecl low, v ee or open data data data v cc or open high lvpecl high or v cc data high low v ee high lvcmos low, v ee , or open data high low v ee high lvcmos high or v cc data data data *pins will default low when left open. 2pin will default high when left open.
NBLVEP16VR http://onsemi.com 3 q figure 3. pinout diagram (top view) d d v bb od_mode en cs_sel qhg v ee qhg v eep en_sel 1 2 3 4 5678 9 10 11 12 13 14 15 16 v cc nc v bb_adj NBLVEP16VR q exposed pad (ep) q figure 4. die map d d v bb od_mode en cs_sel qhg v ee qhg v ee en_sel v cc nc v bb_adj NBLVEP16VR die: 1.16 x 1.19 mm q nc v bb v cc v eep (x) (y) bond pad: 84 m diameter table 4. pin description pin no name i/o description 1 od_mode* lvcmos/lvttl input (see table 3) selectable mode of output disabled level 2 d ecl / lvpecl input clock / data input 3 d ecl / lvpecl input inverted clock / data input 4 v bb reference voltage output reference voltage output 5 en* ecl / lvpecl or lvcmos/lvttl input (see table 3) output enable synchronous with d and d 6 v bb_adj adjust standard v bb levels upward when tied to v cc for 2.5 v power supply. open for 3.3 v and 5 v power supply. 7 v ee negative power supply negative power supply 8 v eep open or tied to v ee (see table 1) optional 10ma current source for qhg and qhg 9 en_sel 2 lvcmos / lvttl input (see table 3) input lvel selector pin for en 10 qhg ecl / lvpecl output inverted high?gain output, gain > 200 11 qhg ecl / lvpecl output high?gain output, gain > 200 12 cs_sel selects q and q current source magnitude (see table 1), open or tied to v ee or v cc 13 v cc positive power supply positive power supply 14 nc no connect no connect 15 q ecl / lvpecl output ecl/lvpecl output for feedback loop 16 q ecl / lvpecl output inverted ecl/lvpecl output for feedback loop ep power supply (opt) exposed pad on package bottom should only be con- nected to v ee or left open *pins will default low when left open. 2pin will default high when left open.
NBLVEP16VR http://onsemi.com 4 applications information the NBLVEP16VR is an ecl/lvpecl oscillator gain stage with high?gain output buffers, selectable output enable and a feedback buffer. the NBLVEP16VR is a solution for crystal oscillators and saw?based voltage?controlled oscillators. design versatility is enhanced with en, a synchronous output enable pin to eliminate runt pulses; en_sel, an input state selector pin offering lvcmos/lvttl or ecl/lvpecl level control of en; and od_mode, an output disable mode state pin which selects the polarity of the high?gain output's disabled state. the NBLVEP16VR q and q outputs are ideal for feedback applications common in crystal oscillator gain blocks. they each have a selectable on?chip pull?down current source. external resistors may be used to increase the pull?down current to a maximum of 25 ma. the qhg and qhg outputs each have an optional on?chip pull?down current source of 10 ma. when v eep is left open, the 10 ma output current sources are disabled and the qhg and qhg outputs operate as standard ecl/lvpecl. when v eep is connected to v ee , the 10 ma current sources are activated. the qhg and qhg pull?down current can be decreased by using a resistor connect from v eep to v ee . see current source truth table for functions and options. the output enable input pin, en, is synchronized with the d and d data input signals in a way that furnishes glitchless gating of the qhg and qhg outputs and allows continuous oscillator operation. for applications that require output enable control, the NBLVEP16VR provides expanded output enable selectability. the logic level of the input state selector pin, en_sel, will determine whether the en pin accepts ecl/lvpecl or lvcmos/lvttl logic levels. the output disable mode state pin, od_mode, adds functional flexibility by giving the designer a choice of the qhg outputs' polarity when these high?gain outputs are disabled. for example, with od_mode low and en low (lvpecl), the input is passed to the outputs and the data output equals the data input. if the d input is low when the en goes high, the next data transition to a high is ignored and qhg remains low and qhg remains high. the next positive transition of the data input is not passed on to the qhg outputs under these conditions. the qhg and qhg outputs remain in their disabled state as long as the en input is held high. the en input has no influence on the q or q outputs and the data inputs are passed on to these outputs whether en is high or low. when the data input is high and en goes high, it will force qhg low and qhg high on the next negative transition of the d input. this configuration is ideal for crystal oscillator applications where the oscillator can be free?running and qhg/qhg gate on and off synchronously without adding extra counts to the output. see truth table and timing diagram for detailed enable functions and options. the NBLVEP16VR provides a v bb and internal 470 bias resistors from d to v bb and d to v bb for ac coupled single?ended or differential input signal(s). the v bb_adj pin is used for 2.5 v single?ended operation when it is connected to v cc . the v bb output current source/sink capability can support a robust 1.5 ma. for single?ended input conditions, the unused dif ferential input is internally connected to v bb as a switching reference voltage. decouple v bb and v cc with a 0.01 f capacitor. this internal v bb will rebias ac coupled input(s). inputs d or d must be signal driven or auto oscillation may result. q q d od_mode en qhg qhg d (pecl) (cmos) en_sel high (open) en_sel low (shorted to v ee ) figure 5. timing diagram
NBLVEP16VR http://onsemi.com 5 attributes characteristics value esd protection human body model machine model charged device model > 2 kv > 150 v > 1 kv moisture sensitivity, indefinite time out of drypack (note 1) level 1 flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in transistor count meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. maximum ratings symbol parameter condition 1 rating unit v cc lvpecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v ?6 v v i lvpecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v 6 ?6 v v i bb v bb current sink/source 1.5 ma i in input current (v in ? v bb ) 470 d, d 5 ma i out output current continuous surge 50 100 ma ma t a operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm c/w c/w jc thermal resistance (junction?to?case) standard board c/w maximum ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum?rated conditions is not implied. functional operation should be restricted to the recommended operating conditions.
NBLVEP16VR http://onsemi.com 6 dc characteristics, lvpecl v cc = 2.5 v, v ee = 0 v (note 2, 6) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current (note 3) 30 35 48 30 38 48 35 40 54 ma v oh output high voltage (note 4) 1340 1670 1340 1670 1340 1670 mv v ol output low voltage (note 4) 620 950 620 950 620 950 mv v ih input high voltage (single?ended) (d, d , en) (notes 5, 6) 1655 2000 1655 2000 1655 2000 mv v il input low voltage (single?ended) (d, d , en) (notes 5, 6) 1050 1395 1050 1395 1050 1395 mv v bb output voltage reference (note 6) 1420 1525 1630 1420 1525 1630 1420 1525 1630 mv v ihcmr input high voltage common mode range (differential configuration) 1.2 2.5 1.2 2.5 1.2 2.5 v i ih input high current (note 5) en 150 150 150 a i il input low current (note 5) en 0.5 0.5 0.5 a note: lvep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 2. input and output parameters vary 1:1 with v cc . 3. v eep and cs_sel open. 4. qhg/qhg outputs loaded with 50 to v cc ? 2.0 v (v eep = open) figure 11 or with optional current source (v eep = v ee ) figure 12. q/q outputs loaded with 8 ma current source (cs_sel = v ee ). 5. en_sel open. 6. v bb_adj tied to v cc for 2.5 v single?ended input operation. dc characteristics, lvpecl v cc = 3.3 v, v ee = 0 v (note 7) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current (note 8) 30 38 48 30 40 48 35 42 54 ma v oh output high voltage (note 9) 2140 2470 2140 2470 2140 2470 mv v ol output low voltage (note 9) 1420 1750 1420 1750 1420 1750 mv v ih input high voltage (single?ended) (d, d , en) (note 10) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (single?ended) (d, d , en) (note 10) 1355 1675 1355 1675 1355 1675 mv v bb output voltage reference 1790 1900 2030 1790 1900 2030 1790 1900 2030 mv v ihcmr input high voltage common mode range (differential configuration) 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current (note 10) en 150 150 150 a i il input low current (note 10) en 0.5 0.5 0.5 a note: lvep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 7. input and output parameters vary 1:1 with v cc . 8. v eep and cs_sel open. 9. qhg/qhg outputs loaded with 50 to v cc ? 2.0 v (v eep = open) figure 11 or with optional current source (v eep = v ee ) figure 12. q/q outputs loaded with 8 ma current source (cs_sel = v ee ). 10. en_sel open.
NBLVEP16VR http://onsemi.com 7 dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 11) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current (note 12) 30 41 48 30 43 48 35 45 54 ma v oh output high voltage (note 13) 3840 4170 3840 4170 3840 4170 mv v ol output low voltage (note 13) 3120 3450 3120 3450 3120 3450 mv v ih input high voltage (single?ended) (d, d , en) (note 14) 3775 4120 3775 4120 3775 4120 mv v il input low voltage (single?ended) (d, d , en) (note 14) 3055 3375 3055 3375 3055 3375 mv v bb output voltage reference 3490 3600 3730 3490 3600 3730 3490 3600 3730 mv v ihcmr input high voltage common mode range (differential configuration) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current (note 14) en 150 150 150 a i il input low current (note 14) en 0.5 0.5 0.5 a note: lvep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 11. input and output parameters vary 1:1 with v cc . 12. v eep and cs_sel open. 13. qhg/qhg outputs loaded with 50 to v cc ? 2.0 v (v eep = open) figure 11 or with optional current source (v eep = v ee ) figure 12. q/q outputs loaded with 8 ma current source (cs_sel = v ee ). 14. en_sel open. dc characteristics, necl v cc = 0 v, v ee = ?5.5v to ?2.375 v (note 15) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current (note 16) 30 38 48 30 40 48 35 42 54 ma v oh output high voltage (note 17) ?1160 ?830 ?1160 ?830 ?1160 ?830 mv v ol output low voltage (note 17) ?1880 ?1550 ?1880 ?1550 ?1880 ?1550 mv v ih input high voltage (single?ended) (d, d , en) (notes 18, 19) ?3.3 v v bb_adj = open ?2.5 v v bb_adj = v cc ?1225 ?845 ?880 ?500 ?1225 ?845 ?880 ?500 ?1225 ?845 ?880 ?500 mv v il input low voltage (single?ended) (d, d , en) (notes 18, 19) ?3.3 v v bb_adj = open ?2.5 v v bb_adj = v cc ?1945 ?1450 ?1625 ?1105 ?1945 ?1450 ?1625 ?1105 ?1945 ?1450 ?1625 ?1105 mv v bb output voltage reference ?3.3 v or ?5.2 v v bb_adj = open ?2.5 v (note 19) v bb_adj = v cc ?1510 ?1080 ?1400 ?975 ?1270 ?870 ?1510 ?1080 ?1400 ?975 ?1270 ?870 ?1510 ?1080 ?1400 ?975 ?1270 ?870 mv v ihcmr input high voltage common mode range (differential configuration) v ee ?5 v v ee +1.2 v ee +2.0 0 v ee +1.2 v ee +2.0 0 v ee +1.2 v ee +2.0 0 v v i ih input high current (note 18) en 150 150 150 a i il input low current (note 18) en 0 .5 0.5 0.5 a note: lvep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. input and output parameters vary 1:1 with v cc . 16. v eep and cs_sel open. 17. qhg/qhg outputs loaded with 50 to v cc ? 2.0 v (v eep = open) figure 11 or with optional current source (v eep = v ee ) figure 12. q/q outputs loaded with 8 ma current source (cs_sel = v ee ). 18. en_sel open. 19. v bb_adj tied to v cc for ?2.5 v single?ended operation.
NBLVEP16VR http://onsemi.com 8 (lvcmos/lvttl dc characteristics v cc = 2.375 v or 5.0 v, v ee = 0 v or v cc = 0 v, v ee = ?2.375 v to ?5.5 v (note 20) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v ih input high voltage v ee +2.0 v cc v ee + 2.0 v cc v ee +2.0 v cc v v il input low voltage v ee v ee +0.8 v ee v ee +0.8 v ee v ee +0.8 v i ih input high current ?150 150 ?150 150 ?150 150 a i il input low current ?150 150 ?150 150 ?150 150 a 20. en_sel = low when en is used as a lvcmos/lvttl input. ac characteristics v cc = 2.375 v to 5.5 v; v ee = 0 v or v cc = 0 v v ee = ?2.375 v to ?5.5 v (note 21) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v outpp differential output (qhg) f out < 1 ghz voltage (peak?to?peak) f out < 2 ghz f out < 2.5 ghz 500 260 210 660 500 400 500 310 210 700 500 380 500 280 190 700 450 330 mv mv t plh , t phl propagation delay (differential) figure 10 d to q (cs_sel = open) figure 10 d to q (cs_sel = v ee ) figure 8 d to qhg (v eep open) figure 9 d to qhg (v eep = v ee ) 215 155 315 320 290 270 390 400 385 395 475 490 215 165 335 335 300 280 410 415 385 405 495 505 230 205 360 360 315 300 440 450 400 445 520 530 ps t s set?up time en to d 0.5 0.5 0.5 ns t h hold time en to d 1.0 1.0 1.0 ns t jitter random clock jitter (rms) 0.5 0.5 0.5 ps t skew duty cycle skew (note 23) 5 20 5 20 5 20 ps v inpp differential input voltage d to qhg (peak?to?peak) (note 22) d to q single?ended configuration d to qhg 25 50 50 800 800 1200 1200 25 50 50 800 800 1200 1200 25 50 50 800 800 1200 1200 mv mv mv t r t f output rise/fall times (20% ? 80%) q, q (cs_sel = v ee or open) qhg, qhg (v eep = v ee or open) 70 90 120 150 300 210 70 90 120 150 300 210 70 90 120 150 300 210 ps dc o output duty cycle (note 24) (qhg) 45 50 55 45 50 55 45 50 55 % 21. qhg/qhg and q/q outputs loaded with ac coupled 50 loads. v eep and cs_sel connected to v ee . 22. v inpp is the minimum differential peak?to?peak input swing for which ac parameters are guaranteed. 23. duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cr oss point of the outputs, (t plh t phl ). 24. assumes 50% input duty cycle, see figures 11 or 12.
NBLVEP16VR http://onsemi.com 9 0 100 200 300 400 500 600 700 800 900 0 500 1000 1500 2000 2500 3000 figure 6. f max /jitter for qhg, qhg output frequency (mhz) 1 2 3 4 5 6 7 8 v outpp (mv) jitter out ps (rms) 9 differential inputs 0 100 200 300 400 500 600 700 800 figure 7. differential gain vs. input voltage (100 mhz) v inpp (mv) qhg/qhg v outpp (mv) 50 40 30 20
NBLVEP16VR http://onsemi.com 10 figure 8. typical termination for output driver v eep open (see application note and8020 ? termination of ecl logic devices.) figure 9. qhg/qhg output loading and termination, v eep = v ee . driver receiver q d q d v ee *r figure 10. q/q output loading and termination, cs_sel open or tied to v ee or v cc driver receiver qhg d qhg d cs_sel (open or tied to v ee ) *r = 2 z o = 100 for 50 transmission lines v eep *r *r = 2 z o = 100 for 50 transmission lines v ee v ee v ee driver receiver qhg d qhg d v eep (open) z o = 50 v tt v tt = v cc ? 2.0 v 50 50 z o = 50 z o = 50 z o = 50 z o = 50 z o = 50
NBLVEP16VR http://onsemi.com 11 figure 11. qhg/qhg device evaluation set?up; v eep = open figure 12. qhg/qhg device evaluation set?up; v eep = v ee driver oscilliscope q q v ee figure 13. q/q device evaluation set?up; cs_sel = v ee or open driver oscilliscope qhg qhg cs_sel (open or tied to v ee ) v eep v ee v ee v ee driver oscilliscope qhg qhg v eep (open) z o = 50 z o = 50 z o = 50 z o = 50 z o = 50 z o = 50 50 50 50 50 50 50
NBLVEP16VR http://onsemi.com 12 q q d d v bb od_mode en cs_sel qhg v ee qhg v eep en_sel q q 0 1 lvcmos/lvttl threshold 470 10 ma ea. 4.0 ma ea. figure 14. typical application vr v bb_adj v bb len latch q d the vcxo, or voltage controlled crystal oscillator, is an oscillator where the output frequency is controlled by the crystal and an external control voltage. the vcxo can have the output frequency change with a change in voltage at a control pin of the oscillator. most, if not all, vcxo's use varactor diodes to vary the frequency. a varactor diode is a semiconductor device that behaves as a variable capacitor when a voltage is applied to it. thus, when a change in the control voltage is applied to the control pin of the oscillator, it causes a change in the capacitance seen by the crystal internal to the oscillator. these changes in the circuit load capacitance cause changes in the oscillator output frequency due to crystal loading.
NBLVEP16VR http://onsemi.com 13 resource reference of application notes an1404 ? eclinps circuit performance at non?standard v ih levels an1406 ? designing with lvpecl (ecl at +5.0 v) and8002 ? marking and date codes and8009 ? eclinps plus spice i/o model kit and8020 ? termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
NBLVEP16VR http://onsemi.com 14 package dimensions qfn?16 case 485g?01 issue a ?t? ?x? note 3 seating plane l a m ?y? b n 0.25 (0.010) t 0.25 (0.010) t j c k r 0.08 (0.003) t g e h f p d 1 4 58 12 9 16 13 dim min max min max inches millimeters a 3.00 bsc 0.118 bsc b 3.00 bsc 0.118 bsc c 0.80 1.00 0.031 0.039 d 0.23 0.28 0.009 0.011 g 0.50 bsc 0.020 bsc h 0.875 0.925 0.034 0.036 j 0.20 ref 0.008 ref k 0.00 0.05 0.000 0.002 l 0.35 0.45 0.014 0.018 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. 3. dimension d applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. e 1.75 1.85 0.069 0.073 f 1.75 1.85 0.069 0.073 m 1.50 bsc 0.059 bsc n 1.50 bsc 0.059 bsc p 0.875 0.925 0.034 0.036 r 0.60 0.80 0.024 0.031 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 NBLVEP16VR/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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